Pathlengths of SPEC Benchmarks for PA-RISC, MIPS, and SPARC
نویسنده
چکیده
The total instruction pathlength and instruction frequency counts are measured for the SPEC89 benchmark programs on the PA-RISC architecture and compared with previously published information for the MIPS and SPARC architectures. The PA-RISC architecture typically requires significantly fewer instructions than the other two architectures for the same benchmark. The differences in counts for instruction sub-classes are compared and used to estimate the actual impact of some PA-RISC architectural features designed for pathlength reduction [2].
منابع مشابه
Microprocessor Standards and Markets , Part 11 : Six Architectural Affiliations
Each of the dominant chip architectures has affiliations with a variety of industry playersfrom chip fabricators to platform vendors. The strength of these affiliations, or keiretsus, will play a key role in determining the general market acceptance of a chip architecture. Intel X86 is the strongest keiretsu based on its immense application availability, volume, and range of products. The Power...
متن کاملPerformance from Architecture: Comparing a RISC and a CISC with Similar Hardware Organization
Performance comparisons across diierent computer archi-tectures cannot usually separate the architectural contribution from various implementation and technology contributions to performance. This paper compares an example implementation from the RISC and CISC architectural schools (a MIPS M/2000 and a Digital VAX 8700) on nine of the ten SPEC benchmarks. The organizational similarity of these ...
متن کاملAliased Register Allocation for Straight-Line Programs Is NP-Complete
Register allocation is NP-complete in general but can be solved in linear time for straight-line programs where each variable has at most one definition point if the bank of registers is homogeneous. In this paper we study registers which may alias: an aliased register can be used both independently or in combination with an adjacent register. Such registers are found in commonly-used architect...
متن کاملA Transformational Approach to Binary Translation of Delayed Branches with Applications to SPARC® and PA-RISC Instructions Sets
A binary translator examines binary code for a source machine, optionally builds an intermediate representation, and generates code for a target machine. Understanding what to do with delayed branches in binary code can involve tricky case analyses, e.g., if there is a branch instruction in a delay slot. Correctness of a translation is of utmost importance. This paper presents a disciplined met...
متن کاملA Tale of Two Processors: Revisiting the RISC-CISC Debate
The contentious debates between RISC and CISC have died down, and a CISC ISA, the x86 continues to be popular. Nowadays, processors with CISC-ISAs translate the CISC instructions into RISC style micro-operations (eg: uops of Intel and ROPS of AMD). The use of the uops (or ROPS) allows the use of RISC-style execution cores, and use of various micro-architectural techniques that can be easily imp...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 1993